The present invention relates to memory systems. In particular, the present invention relates to the renumbering of arrays within memory systems.
To reduce manufacturing costs, manufacturers of integrated circuits search for ways to improve yields and reduce the rejection rate for defective individual parts. One method of reducing the rejection rate is to provide redundant or auxiliary circuit components on the integrated circuit. This method is practical where testing can locate the defective component, and the circuit is readily reconfigurable to substitute a redundant equivalent for the defective component. This method is widely used in integrated circuit memory arrays such as random access memories.
Memory circuits are characterized by the regular repetition of multitudes of memory cells. The location of each memory cell is defined by a unique address which typically identifies a particular row and column in the memory matrix arrays. The memory circuit includes row and column decoders that decode different combinations of signals at an address input to the memory circuit. Memory circuits provide for redundancy by including on the same circuit several duplicate rows and/or columns of memory cells to replace any row or column having defective memory cells. Separate decoders are provided for the redundant rows or columns that are programmable using programming elements such as fusible links. Once the integrated circuit is tested and the locations of the defective memory cells are determined, the programmable redundancy decoders are programmed to decode those addresses that correspond to the rows or columns with defective cells. The defective rows or columns are subsequently disabled. This way every time a defective row or column is addressed, a redundant equivalent is selected instead.
Unfortunately, when a memory array has more defective rows or columns than redundant equivalents, the entire memory device must be discarded. Discarding chips having defective bits is wasteful, inefficient and costly.
Accordingly, it would be desirable to provide a memory design which allows a chip with one or more defective memory arrays to be used rather than discarded.